The present invention relates to a circuit for generating internal supply voltage for use in a high density semiconductor memory device. In particular, the present invention relates to a circuit for generating internal supply voltage wherein the output voltage generated therefrom increases in response to increase of the temperature.
At recent, in a semiconductor memory device with high memory capacity, it is required to supply a metal oxide silicon (hereafter referred to as MOS) transistor below a micron unit level with low supply voltage lower than the external supply voltage of 5 V which is generally supplied in computer systems. For this end, an internal supply voltage generator must be prepared in semiconductor chips in addition to a memory circuit so as to supply the low internal supply voltage. For instance, a semiconductor dynamic random access memory (hereinafter referred to as "DRAM" device over 16 Mbit level necessarily includes the internal supply voltage generator in order to obtain a high reliability of the memory device.
A prior art internal supply voltage generator and the characteristics thereof are well disclosed with reference to FIGS. 1 to 3. Referring to FIG. 1, the conventional internal supply voltage generator 100 includes of a reference voltage generator 50, a comparator 60 and an output circuit 70. Shown in FIG. 2 are the characteristics of the internal supply voltage generator of FIG. 1, in comparison with the external supply voltage. Furthermore, another embodiment of the reference voltage generator 50 of FIG. 1 is described in FIG. 3.
Referring again to FIG. 1, the internal supply voltage generator 100 has the reference voltage generator 50 and the output circuit 70 which includes a p-channel metal oxide semiconductor (hereinafter referred to as "PMOS") transistor 10 serving as a variable resistor. The voltage output from the reference voltage generator 50 and the output circuit 70 are then compared at the comparator 60 which is a differential amplifier for controlling the voltage applied to the gate of the PMOS transistor 10. The reference voltage generator 50 has first and second resistors R.sub.1, R.sub.2 connected in series between the external supply voltage and the ground level, to generate reference voltage V.sub.ref through a connection node 3. The comparator 60 has first and second NMOS transistors 6, 7 forming a differential amplifier, a third NMOS transistor 8 serving as a constant current source, and a first and second PMOS transistors 4, 5 forming a current mirror load stage. Moreover, the PMOS transistor 10 has the source connected to the external supply voltage Vcc.sub.ext, and the drain connected to the internal supply voltage Vcc.sub.int of an output node 11. In the drawing, the reference voltage V.sub.ref is applied to the gate to the first NMOS transistor 6 of the comparator 60. In the event that the load current flow is formed from the output node 11 to memory circuit (not shown), a voltage drop occurs at the PMOS transistor 10 of the output circuit 70. As a result, the internal supply voltage is set to a voltage level lower than the external supply voltage. At the same moment, the comparator 60 controls the gate voltage of the PMOS transistor 10 so as to keep the internal supply voltage level identical to the reference voltage V.sub.ref level.
The internal supply voltage generator must keep a constant internal supply voltage regardless of the change of the external supply voltage in order to obtain high reliability of the semiconductor memory device. Undesirably, however, the conventional internal supply voltage generator 100 of FIG. 1 has the voltage difference .DELTA.V as shown in FIG. 2, in response to the increase of the external supply voltage. The foregoing problem is caused by the fact that the reference voltage V.sub.ref from the reference voltage generator 50 is ##EQU1## therefore, the reference voltage V.sub.ref increases as the external supply voltage increases, thereby increasing the internal supply voltage. Accordingly, the reliability of the semiconductor may be reduced.
Referring to FIG. 3, the reference voltage generator 50 includes of a first to third PMOS transistors 12, 13, 14 connected in series to each other, and fourth and fifth PMOS transistors 15, 16 connected in series to each other, the first to third PMOS transistors being connected in parallel to the fourth and fifth PMOS transistors. The gates and drains of first to fifth PMOS transistors 12-16 each are diode-connected and, further, the gate of the fourth PMOS transistor 15 is connected to the source of the third PMOS transistor 14. The source of the third PMOS transistor 14 is coupled so as to set the gate voltage level of the fourth PMOS transistor 15 to ##EQU2## the source of the fourth PMOS transistor 15 becoming an output node 17, by which the reference voltage generator 50 generates the reference voltage V.sub.ref, through the output mode 17. As the temperature increases, however, the threshold voltage V.sub.th of the respective PMOS transistors in the reference voltage generator 50 shown in FIG. 3 is reduced. Therefore, the reference voltage V.sub.ref will also be reduced. If the reference voltage is reduced, the internal supply voltage will also be reduced, causing the semiconductor memory device to operate at a low speed.